Siemens delivers new verification system
by CM Staff
Expansion of the customer-proven Veloce family sets new standard in hardware-assisted verification
Siemens Digital Industries Software today unveiled its next-generation Veloce hardware-assisted verification system for the verification of next-generation integrated circuit (IC) designs.
This approach to managing verification cycles emphasizes running market-specific, real-world workloads, frameworks, and benchmarks early in the verification cycle for power and performance analysis. This enables customer-built virtual SoC models early in the cycle and the integration to begin running real-world firmware and software on Veloce Strato+ for deep-visibility to the lowest level of hardware. Customers can then move the same design to Veloce Primo to validate the software/hardware interfaces and execute application-level software while running closer to actual system speeds. To make this approach as efficient as possible, Veloce Strato+ and Veloce Primo use the same RTL, the same virtual verification environment, the same transactors and models to maximize the reuse of verification collateral, environment and test content. This is a necessary foundation for a seamless methodology.
“As we enter the new semiconductor mega-cycle, the era of software-centric SoC design requires a dramatic change in functional verification systems to address new requirements,” said Ravi Subramanian, Senior Vice President and General Manager, Siemens EDA, in a statement. “The introduction of the next-generation Veloce system that addresses these key new requirements is a direct result of the focused investment from Siemens to offer our customers a complete, integrated system with a clear roadmap for the next decade. With today’s announcement, we are establishing a new standard for a system that is capable of supporting the new verification requirements across a diverse set of industries-spanning computing and storage, AI/ML, 5G, networking, and automotive.”
Innovation in chip, system, and software design enables Veloce Strato+ to deliver to the capacity roadmap published in 2017 when the Veloce Strato platform was introduced. The innovative design and manufacturing of the Crystal 3+—a new, proprietary 2.5D chip—increases system capacity by 1.5x over the previous Veloce Strato system. This innovation enables Veloce Strato+ to lead in the emulation market with marketing-leading available capacity of 15B gates. This capacity, which is the largest effective capacity available today, is now in use at multiple Veloce Strato+ customers.
The Veloce Strato system is also expanding the list of qualified processors by adding the AMD EPYC™ 7003 series processor, starting today. These new processors are fully qualified to run with the Veloce Strato systems as run time hosts and co-model hosts.
Veloce Primo and Veloce proFPGA represent the industry’s most powerful and versatile approach to FPGA prototyping. The enterprise-level FPGA prototyping system, Veloce Primo, simultaneously delivers outstanding performance, with capacity scaling up to 320 FPGAs and a consistent working model with Veloce Strato in terms of software workloads, design models and front-end compilation technology. This fundamental alignment between emulation and prototyping contributes to reducing the cost of verification by leveraging the right tool for the task where the emulation and the prototyping work together as complimentary solutions for a better outcome in the shortest cycle.